The present disclosure relates to a circuit and method for generating column path control signals in a semiconductor device, wherein the column path control signals can be generated under the condition in which they have been influenced by the same process, voltage, and temperature (PVT) characteristic variation of CMOS transistors.
In general, a semiconductor device, in particular, a DRAM, needs various column path control signals for execution of a read or write operation. For example, column path control signals required for execution of a read or write operation in a DRAM include local input/output line precharge signals (for example, liopcg and lio_pcgback in FIG. 1) for controlling an operation of precharging signals on local input/output lines, a local input/output line reset signal (for example, lio_rst in FIG. 1) for equalizing the levels of the local input/output lines in response to the local input/output line precharge signals (for example, liopcg and lio_pcgback in FIG. 1), an output enable signal (for example, yi in FIG. 1) enabling transfer of bit line signals amplified by a sense amplifier to the local input/output lines in accordance with a read command, an amplification control signal (for example, iosa1 in FIG. 1) for controlling an operation of amplifying the signals on the local input/output lines in the read operation, a latch control signal (for example, iosa2 in FIG. 1) for controlling an operation of latching the amplified signals on the local input/output lines in the read operation, and a pull-up/pull-down control signal (for example, bwen in FIG. 1) for controlling a pull-up/pull-down operation for global input/output lines (for example, gio in FIG. 1) in a write operation. These control signals can be generated based on the same strobe signal.
FIG. 1 illustrates a configuration of a conventional column path control signal generating circuit.
The column path control signal generating circuit shown in FIG. 1 generates a plurality of column path control signals (liopcg, lio_rst, lio_pcgback, bwen, yi, iosal1, and iosa2) for a read or write operation in a DRAM, in accordance with parallel processing of a strobe signal. The column path control signal generating circuit of FIG. 1 includes first to fifth delay units 1 to 5 each adapted for delaying the strobe signal for a certain period, independently of the remaining delay units, inverters IV3 to IV12 connected in pairs to the first to fifth delay units 1 to 5, and delays 6 and 7. In accordance with the independent delay operations of the delay units 1 to 5, and delay operations of the delays 6 and 7, the column path control signals liopcg, lio_rst, lio_pcgback, bwen, yi, iosal1, and iosa2 are generated.
However, CMOS transistors included in the first to fifth delay units 1 to 5, and inverters IV3 to IV12, respectively, may exhibit different variations in process, voltage and temperature (PVT) characteristics. For this reason, the timings of the column path control signals liopcg, lio_rst, lio_pcgback, bwen, yi, iosal1, and iosa2 generated in a parallel manner through the first to fifth delay units 1 to 5 and inverters IV3 to IV12 may not coincide due to the different PVT characteristic variations of the associated CMOS transistors. As a result, there is a problem in that an erroneous read or write operation is carried out.
An improved approach for generating the column path control signals is needed.